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signal integrity Engineer

signal integrity Engineer

Perform signal integrity analysis on high speed interfaces for memory and processor subsystem. Clear understanding of signal and noise issues in high speed designs. Possess ability to work with cross functional teams in physical design, board design and systems teams.

Updated: 2011-Oct-01 12:49 PM

Industry: IT Products, SemiconductorRole: Signal Integrity Engineer

Experience Level: 2.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: signal integrity high speed designs Ansoft HFSS/ Nexxsim /Hspice statistical analysis I/O design electromagnetic theory

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signal integrity Engineer

signal integrity Engineer

Perform signal integrity analysis on high speed interfaces for memory and processor subsystem. Clear understanding of signal and noise issues in high speed designs. Possess ability to work with cross functional teams in physical design, board design and systems teams.

Updated: 2011-Sep-30 05:50 PM

Industry: IT Products, SemiconductorRole: Signal Integrity Engineer

Experience Level: 2.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: signal integrity high speed designs Ansoft HFSS/ Nexxsim /Hspice statistical analysis I/O design electromagnetic theory

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Physical Design

Physical Design

This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization. Individual must have hands on PD experience with industry standard tools.

Updated: 2011-Oct-01 12:57 PM

Industry: SemiconductorRole: Physical Design Engineer

Experience Level: 6.0 to 10.0 yrsLocation: (India)

Keywords: Physical Design unit level integration floorplanning timing closure Cadence virtuoso tool

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Physical Design

Physical Design

This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization. Individual must have hands on PD experience with industry standard tools.

Updated: 2011-Oct-01 12:56 PM

Industry: SemiconductorRole: Physical Design Engineer

Experience Level: 6.0 to 10.0 yrsLocation: (India)

Keywords: Physical Design unit level integration floorplanning timing closure Cadence virtuoso tool

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Physical Design

Physical Design

This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization. Individual must have hands on PD experience with industry standard tools.

Updated: 2011-Oct-01 12:47 PM

Industry: SemiconductorRole: Physical Design Engineer

Experience Level: 6.0 to 10.0 yrsLocation: (India)

Keywords: Physical Design unit level integration floorplanning timing closure Cadence virtuoso tool

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Physical Design

Physical Design

This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization. Individual must have hands on PD experience with industry standard tools.

Updated: 2011-Sep-30 05:55 PM

Industry: SemiconductorRole: Physical Design Engineer

Experience Level: 6.0 to 10.0 yrsLocation: (India)

Keywords: Physical Design unit level integration floorplanning timing closure Cadence virtuoso tool

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